After the PCB wiring is completed, the DRC check is performed. The prawn help to see if there is a problem.

Protel Design System Design Rule Check

PCB File : Documents\xg_yz_144v\DL_201_02_V6(3700131)-2018-06-14.PCB

Date     : 30 -Dec-2018

Time     : 09:39:00

 

Processing Rule : Width Constraint (Min=0.254mm) (Max=3.99999mm) (Prefered=0.5mm) (On the board )

Rule Violations :0

 

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ), (On the board )

Rule Violations :0

 

Processing Rule : Broken- Net Constraint ( (On the board ) )

   Violation         Net VCC_24V   is broken into 3 sub-nets. Routed To 94.44%

     Subnet : Q310-2   

     Subnet : Q306-2   

     Subnet : Q302-2   R338-1   

Rule Violations :1

 

Processing Rule : Clearance Constraint (Gap =0.254mm) (On the board ), (On the b Oard )

Rule Violations :0

 

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the Board )

   Violation         Pad Free-0(195.87mm,244.5mm)  MultiLayer  Actual Hole Size = 3.3mm

   Violation         Pad Free-0(178.25mm,244.67mm)  MultiLayer  Actual Hole Size = 3.3mm

   Violation         Pad Free-1(213.78mm,244.62mm)  MultiLayer  Actual Hole Size = 3.3mm

Rule Violations :3

 

Processing Rule : Width Constraint (Min=0.254mm) (Max=3.99999mm) (Prefered=0.3mm) (On the board )

Rule Violations :0

 

Violations Detected : 4

Time Elapsed        : 00:00:01

Addition: Protel Design System Design Rules Check the PCB file: Documents \ xg_yz_144v \ DL_201_02_V6(3700131)-2018-06-14. PCB Date: December 30, 2018 Time: 09:39 :00 Machining rule: Width constraint (minimum = 0.254mm) (maximum = 3.99999mm) (preferred = 0.5mm) (on board) rule violation: 0 Processing rule: short circuit constraint (allow = not allowed) (on the board), (On-board) Rule violation: 0 Processing rule: Broken network constraint ((on board)) Violation network VCC_24V is divided into 3 subnets. Route to 94.44% Subnet: Q310-2 Subnet: Q306-2 Subnet: Q302-2 R338-1 Violation Rule: 1 Processing Rule: Clearance Constraint (Gap = 0.254mm) (on board), (on board Rule violation: 0 Machining rule: hole size constraint (minimum = 0.0254mm) (maximum = 2.54mm) (on board) crash pad Free-0 (195.87mm, 244.5mm) MultiLayer actual hole size = 3.3mm violation pad Free -0 (178.25mm, 244.67mm) MultiLayer actual hole size = 3.3mm Violation Pad Free-1 (213.78mm, 244.62mm) MultiLayer actual hole size = 3.3mm violation rule: 3 Processing rule: width constraint (min = 0.254mm) (maximum = 3.99999mm) (preferred = 0.3mm) (on board) rule violation: 0 detected violation: 4 elapsed time: 00:00:01